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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adv7127 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 cmos, 240 mhz 10-bit high speed video dac functional block diagram d9Cd0 gnd r set i out i out comp adv7127 v ref voltage* reference circuit pdown * powerC down mode v aa 10 dac 10 data register clock psave *on tssop version only features 240 msps throughput rate 10-bit d/a converters sfdr C70 db typ: f clk = 50 mhz; f out = 1 mhz C53 db typ: f clk = 140 mhz; f out = 40 mhz rs-343a/rs-170 compatible output complementary outputs dac output current range: 2 ma to 26 ma ttl compatible inputs internal voltage reference (1.23 v) on tssop package single supply +5 v/+3.3 v operation 28-lead soic package and 24-lead tssop package low power dissipation (30 mw min @ 3 v) low power standby mode (10 mw min @ 3 v) power-down mode (60 mw min @ 3 v) power-down mode available on tssop package industrial temperature range (C40 8 c to +85 8 c) applications digital video systems (1600 3 1200 @ 100 hz) high resolution color graphics digital radio modulation image processing instrumentation video signal reconstruction direct digital synthesis (dds) wireless lan general description the adv7127 (adv ? ) is a high speed, digital-to-analog con- vertor on a single monolithic chip. it consists of a 10-bit, video d/a converter with on-board voltage reference, comple- mentary outputs, a standard ttl input interface and high impedance analog output current sources. the adv7127 has a 10-bit wide input port. a single +5 v/ +3.3 v power supply and clock are all that are required to make the part functional. the adv7127 is fabricated in a cmos process. its monolithic cmos construction ensures greater functionality with lower power dissipation. the adv7127 is available in a small outline 28-lead soic or 24-lead tssop package. the adv7127 tssop package also has a power-down mode. both adv7127 packages have a power standby mode. the adv7127 tssop package has an on-board voltage refer- ence circuit. the adv7127 soic package requires an external reference. product highlights 1. 240 msps throughput. 2. guaranteed monotonic to 10 bits. 3. compatible with a wide variety of high resolution color graphics systems including rs-343a and rs-170a. adv is a registered trademark of analog devices, inc.
C2C rev. 0 adv7127Cspecifications 5 v soic specifications parameter min typ max units test conditions static performance resolution (each dac) 10 bits integral nonlinearity (bsl) C1 0.4 +1 lsb differential nonlinearity C1 0.25 +1 lsb guaranteed monotonic digital and control inputs input high voltage, v ih 2v input low voltage, v il 0.8 v input current, i in C1 +1 m av in = 0.0 v or v aa psave pull-up current 20 m a input capacitance, c in 10 pf analog outputs output current 2.0 18.5 ma output compliance range, v oc 0 +1.4 v output impedance, r out 100 k w output capacitance, c out 10 pf i out = 0 ma offset error C0.025 +0.025 % fsr tested with dac output = 0 v gain error 2 C5.0 +5.0 % fsr fsr = 17.62 ma voltage reference (ext.) reference range, v ref 1.12 1.235 1.35 v power dissipation digital supply current 3 3.4 9 ma f clk = 50 mhz digital supply current 3 10.5 15 ma f clk = 140 mhz digital supply current 3 18 25 ma f clk = 240 mhz analog supply current 33 37 ma r set = 560 w analog supply current 5 ma r set = 4933 w standby supply current 4 2.1 5.0 ma psave = low, digital and control inputs at v aa power supply rejection ratio 0.1 0.5 %/% notes 1 temperature range t min to t max : C40 c to +85 c at 50 mhz and 140 mhz, 0 c to +70 c at 240 mhz. 2 gain error = ((measured (fsc)/ideal (fsc) C1) 100), where ideal = v ref /r set k (3ffh) and k = 7.9896. 3 digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 v and v dd . 4 these max/min specifications are guaranteed by characterization to be over 4.75 v to 5.25 v range. specifications subject to change without notice. (v aa = +5 v 6 5%, v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications t min to t max 1 unless otherwise noted, t j max = 110 8 c)
C3C rev. 0 adv7127 5 v tssop specifications parameter min typ max units test conditions static performance resolution (each dac) 10 bits integral nonlinearity (bsl) C1 0.4 +1 lsb differential nonlinearity C1 0.25 +1 lsb guaranteed monotonic digital and control inputs input high voltage, v ih 2v input low voltage, v il 0.8 v pdown input high voltage 2 3v pdown input low voltage 2 1v input current, i in C1 +1 m av in = 0.0 v or v aa psave pull-up current 20 m a pdown pull-up current 20 m a input capacitance, c in 10 pf analog outputs output current 2.0 18.5 ma output compliance range, v oc 0 +1.4 v output impedance, r out 100 k w output capacitance, c out 10 pf i out = 0 ma offset error C0.025 +0.025 % fsr tested with dac output = 0 v gain error 3 C5.0 +5.0 % fsr fsr = 17.62 ma voltage reference (ext. and int.) 4 reference range, v ref 1.12 1.235 1.35 v power dissipation digital supply current 5 1.5 3 ma f clk = 50 mhz digital supply current 5 46 ma f clk = 140 mhz digital supply current 5 6.5 10 ma f clk = 240 mhz analog supply current 23 27 ma r set = 560 w analog supply current 5 ma r set = 4933 w standby supply current 6 3.8 6 ma psave = low, digital and control inputs at v aa pdown supply current 2 1ma power supply rejection ratio 0.1 0.5 %/% notes 1 temperature range t min to t max : C40 c to +85 c at 50 mhz and 140 mhz, 0 c to +70 c at 240 mhz. 2 this power-down feature is only available on the adv7127 in the tssop package. 3 gain error = ((measured (fsc)/ideal (fsc) C1) 100), where ideal = v ref /r set k (3ffh ) and k = 7.9896. 4 internal voltage reference is available only on the adv7127 tssop package. 5 digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 v and v dd . 6 these max/min specifications are guaranteed by characterization to be over 4.75 v to 5.25 v range. specifications subject to change without notice. (v aa = +5 v 6 5%, v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications t min to t max 1 unless otherwise noted, t j max = 110 8 c)
C4C rev. 0 adv7127Cspecifications 3.3 v soic specifications 1 parameter min typ max units test conditions static performance resolution (each dac) 10 bits r set = 680 w integral nonlinearity (bsl) C1 0.5 +1 lsb r set = 680 w differential nonlinearity C1 0.25 +1 lsb r set = 680 w digital and control inputs input high voltage, v ih 2.0 v input low voltage, v il 0.8 v input current, i in C1 +1 m av in = 0.0 v or v dd psave pull-up current 20 m a input capacitance, c in 10 pf analog outputs output current 2.0 18.5 ma output compliance range, v oc 0 +1.4 v output impedance, r out 70 k w output capacitance, c out 10 pf offset error 0 0 % fsr tested with dac output = 0 v gain error 3 0 % fsr fsr = 17.62 ma voltage reference (ext.) reference range, v ref 1.12 1.235 1.35 v power dissipation digital supply current 4 2.2 5.0 ma f clk = 50 mhz digital supply current 4 6.5 12.0 ma f clk = 140 mhz digital supply current 4 11 15 ma f clk = 240 mhz analog supply current 32 35 ma r set = 560 w analog supply current 5 ma r set = 4933 w standby supply current 2.4 5.0 ma psave = low, digital and control inputs at v dd power supply rejection ratio 0.1 0.5 %/% notes 1 these max/min specifications are guaranteed by characterization to be over 3.0 v to 3.6 v range. 2 temperature range t min to t max : C40 c to +85 c at 50 mhz and 140 mhz, 0 c to +70 c at 240 mhz. 3 gain error = ((measured (fsc)/ideal (fsc) C1) 100) , where ideal = v ref /r set k (3ffh) and k = 7.9896. 4 digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 v and v dd . specifications subject to change without notice. (v aa = +3.0 vC3.6 v, v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications t min to t max 2 unless otherwise noted, t j max = 110 8 c)
C5C rev. 0 adv7127 3.3 v tssop specifications 1 parameter min typ max units test conditions static performance resolution (each dac) 10 bits r set = 680 w integral nonlinearity (bsl) C1 0.5 +1 lsb r set = 680 w differential nonlinearity C1 0.25 +1 lsb r set = 680 w digital and control inputs input high voltage, v ih 2.0 v input low voltage, v il 0.8 v pdown input high voltage 3 2.1 v pdown input low voltage 3 0.6 v input current, i in C1 +1 m av in = 0.0 v or v dd psave pull-up current 20 m a input capacitance, c in 10 pf analog outputs output current 2.0 18.5 ma output compliance range, v oc 0 +1.4 v output impedance, r out 70 k w output capacitance, c out 10 pf offset error 0 0 % fsr tested with dac output = 0 v gain error 4 0 % fsr fsr = 17.62 ma voltage reference (ext.) reference range, v ref 1.12 1.235 1.35 v voltage reference (int.) 5 reference range, v ref 1.235 v power dissipation digital supply current 6 12 ma f clk = 50 mhz digital supply current 6 2.5 4.5 ma f clk = 140 mhz digital supply current 6 46 ma f clk = 240 mhz analog supply current 22 25 ma r set = 560 w analog supply current 5 ma r set = 4933 w standby supply current 2.6 3 ma psave = low, digital and control inputs at v dd pdown supply current 20 m a power supply rejection ratio 0.1 0.5 %/% notes 1 these max/min specifications are guaranteed by characterization to be over 3.0 v to 3.6 v range. 2 temperature range t min to t max : C40 c to +85 c at 50 mhz and 140 mhz, 0 c to +70 c at 240 mhz. 3 this power-down feature is only available on the adv7127 in the tssop package. 4 gain error = ((measured (fsc)/ideal (fsc) C1) 100), where ideal = v ref /r set k (3ffh) and k = 7.9896. 5 internal voltage reference is available only on the adv7127 tssop package. 6 digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 v and v dd . specifications subject to change without notice. (v aa = +3.0 vC3.6 v, v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications t min to t max 2 unless otherwise noted, t j max = 110 8 c)
C6C rev. 0 adv7127Cspecifications 5 v/3.3 v dynamic specifications parameter min typ max units dac performance glitch impulse 2, 3 10 pvs data feedthrough 2, 3 22 db clock feedthrough 2, 3 33 db notes 1 these max/min specifications are guaranteed by characterization. 2 ttl input values are for 0 v and 3 v with input rise/fall times 3 ns, measured at the 10% and 90% points. timing reference points at 50% for inputs and outputs. 3 clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. glitch impulse includ es clock and data feedthrough. specifications subject to change without notice. (v aa = (3 vC5.25 v) 1 , v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications are for t a = +25 8 c unless otherwise noted, t j max = 110 8 c) 5 v timing specifications 1 parameter min typ max units condition analog outputs analog output delay, t 6 5.5 ns analog output rise/fall time, t 7 4 1.0 ns analog output transition time, t 8 5 15 ns analog output skew, t 9 6 12 ns clock control f clk 7 0.5 50 mhz 50 mhz grade f clk 7 0.5 140 mhz 140 mhz grade f clk 7 0.5 240 mhz 240 mhz grade data and control setup, t 1 1.5 ns data and control hold, t 2 2.5 ns clock pulsewidth high, t 4 1.875 1.1 ns f max = 240 mhz clock pulsewidth low t 5 1.875 1.25 ns f max = 240 mhz clock pulsewidth high t 4 2.85 ns f max = 140 mhz clock pulsewidth low t 5 2.85 ns f max = 140 mhz clock pulsewidth high t 4 8.0 ns f max = 50 mhz clock pulsewidth low t 5 8.0 ns f max = 50 mhz pipeline delay, t pd 6 1.0 1.0 1.0 clock cycles psave up time, t 10 6 210 ns pdown up time, t 11 8 320 ns notes 1 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ) 0 for both 5 v and 3.3 v supplies. 2 these maximum and minimum specifications are guaranteed over this range. 3 temperature range: t min to t max : C40 c to +85 c at 50 mhz and 140 mhz, 0 c to +70 c at 240 mhz. 4 rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a ful l-scale transition. 5 measured from 50% point of full-scale transition to 2% of final value. 6 guaranteed by characterization. 7 f clk max specification production tested at 125 mhz and 5 v. limits specified here are guaranteed by characterization. 8 this power-down feature is only available on the adv7127 in the tssop package. specifications subject to change without notice. (v aa = +5 v 6 5% 2 , v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications t min to t max 3 unless otherwise noted, t j max = 110 8 c)
adv7127 C7C rev. 0 3.3 v timing specifications 1 parameter min typ max units condition analog outputs analog output delay, t 6 7.5 ns analog output rise/fall time, t 7 4 1.0 ns analog output transition time, t 8 5 15 ns analog output skew, t 9 6 12 ns clock control f clk 7 50 mhz 50 mhz grade f clk 7 140 mhz 140 mhz grade f clk 7 240 mhz 240 mhz grade data and control setup, t 2 6 1.5 ns data and control hold, t 2 6 2.5 ns clock pulsewidth high, t 4 1.1 ns f max = 240 mhz clock pulsewidth low t 5 6 1.4 ns f max = 240 mhz clock pulsewidth high t 4 6 2.85 ns f max = 140 mhz clock pulsewidth low t 5 6 2.85 ns f max = 140 mhz clock pulsewidth high t 4 6 8.0 ns f max = 50 mhz clock pulsewidth low t 5 6 8.0 ns f max = 50 mhz pipeline delay, t pd 6 1.0 1.0 1.0 clock cycles psave up time, t 10 6 410 ns pdown up time, t 11 8 320 ns notes 1 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ) 0 for both 5 v and 3.3 v supplies. 2 these maximum and minimum specifications are guaranteed over this range. 3 temperature range: t min to t max : C40 c to +85 c at 50 mhz and 140 mhz, 0 c to +70 c at 240 mhz. 4 rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a ful l-scale transition. 5 measured from 50% point of full-scale transition to 2% of final value. 6 guaranteed by characterization. 7 f clk max specification production tested at 125 mhz and 5 v limits specified here are guaranteed by characterization. 8 this power-down feature is only available on the adv7127 in the tssop package. specifications subject to change without notice. clock data t 4 t 5 t 7 t 8 notes: 1. output delay ( t 6 ) measured from the 50% point of the rising edge of clock to the 50% point of full scale transition. 2. output rise/fall time ( t 7 ) measured between the 10% and 90% points of full scale transition. 3. transition time ( t 8 ) measured from the 50% point of full scale transition to within 2% of the final output value. t 2 analog outputs (i out , ) digital inputs (d9Cd0) t 3 t 1 t 6 i out figure 1. timing diagram (v aa = +3.0 vC3.6 v 2 , v ref = 1.235 v, r set = 560 v . all specifications t min to t max 3 unless otherwise noted, t j max = 110 8 c)
adv7127 C8C rev. 0 ordering guide 1 speed options package 50 mhz 140 mhz 240 mhz r-28 2 adv7127kr50 adv7127kr140 adv7127jr240 ru-24 3 adv7127kru50 adv7127kru140 adv7127jru240 notes 1 50 mhz and 140 mhz devices are specified for C40 c to +85 c operation; 240 mhz devices are specified for 0 c to +70 c. 2 soic package. 3 tssop package. absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v voltage on any digital pin . . . . . gnd C 0.5 v to v aa + 0.5 v ambient operating temperature (t a ) . . . . . C40 c to +85 c storage temperature (t s ) . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c vapor phase soldering (1 minute) . . . . . . . . . . . . . . . . 220 c i out to gnd 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to v aa notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. pin configurations 24-lead tssop 28-lead soic top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 adv7127 nc = no connect nc pdown d8 d7 d6 v aa d1 d2 d5 d4 d3 nc clock gnd gnd v aa d0 psave r set v ref i out comp d9 i out top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 adv7127 v aa v aa v aa d9 d8 v aa d2 d3 d4 d7 d6 d5 v aa v aa clock gnd gnd v aa i out v aa psave v aa r set v aa comp v ref d1 d0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv7127 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
adv7127 C9C rev. 0 pin function descriptions pin mnemonic function clock clock input (ttl compatible). the rising edge of clock latches the r0Cr9, g0Cg9, b0Cb9, sync and blank pixel and control inputs. it is typically the pixel clock rate of the video system. clock should be driven by a dedicated ttl buffer. d0Cd9 data inputs (ttl compatible). data is latched on the rising edge of clock. d0 is the least significant data bit. unused data inputs should be connected to either the regular pcb power or ground plane. i out current output. this high impedance current source is capable of directly driving a doubly terminated 75 w coaxial cable. r set full-scale adjust control. a resistor (r set ) connected between this pin and gnd controls the magnitude of the full-scale video signal. note that the ire relationships are maintained, regardless of the full-scale output current. the relationship between r set and the full-scale output current on i out is given by: i out ( ma ) = 7968 v ref ( v )/ r set ( w ) comp compensation pin. this is a compensation pin for the internal reference amplifier. a 0.1 m f ceramic capacitor must be connected between comp and v aa . v ref voltage reference input. an external 1.23 v voltage reference must be connected to this pin. the use of an exter- nal resistor divider network is not recommended. a 0.1 m f decoupling ceramic capacitor should be connected between v ref and v aa . v aa analog power supply (5 v 5%). all v aa pins on the adv7127 must be connected. gnd ground. all gnd pins must be connected. i out differential current output. capable of directly driving a doubly terminated 75 w load. if not required, this out- put should be tied to ground. psave power save control pin. the part is put into standby mode when psave is low. the internal voltage reference circuit is still active on the tssop in this case. pdown power-down control pin (24-lead tssop only). the adv7127 completely powers down, including the voltage reference circuit, when pdown is low. terminology color video (rgb) this usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures within the usual spectrum. in rgb monitors, three dacs are required, one for each color. gray scale the discrete levels of video signal between reference black and reference white levels. a 10-bit dac contains 1024 different levels, while an 8-bit dac contains 256. raster scan the most basic method of sweeping a crt one line at a time to generate and display images. reference black level the maximum negative polarity amplitude of the video signal. reference white level the maximum positive polarity amplitude of the video signal. video signal that portion of the composite video signal which varies in gray scale levels between reference white and reference black. also referred to as the picture signal, this is the portion that may be visually observed.
adv7127 C10C rev. 0 5 vCtypical performance characteristics (v aa = +5 v, v ref = 1.235 v, i out = 17.62 m a, 50 v doubly terminated load, differential output loading, t a = +25 8 c) frequency C mhz 70 0 0.1 100 1.0 2.51 5.04 20.2 40.4 60 50 40 20 10 30 sfdr (de) sfdr (se) sfdr C dbc figure 2. sfdr vs. f out @ f clock = 140 mhz (single-ended and differential) f clock C mhz 76 74 58 0 160 50 100 140 68 64 62 60 72 70 66 4th harmonic 2nd harmonic 3rd harmonic thd C dbc figure 5. thd vs. f clock @ f out = 2 mhz (2nd, 3rd and 4th harmonics) v aa = 5v 1 2 C5.0 C45.0 C85.0 0khz start 35.0mhz 70.0mhz stop sfdr C dbm clk = 140mhz f out = 2.5mhz sing o/p figure 8. sfdr (single-tone) @ f clock = 140 mhz (f out1 = 2 mhz) frequency C mhz 80 0 70 40 30 20 10 60 50 0.1 100 1.0 2.51 5.04 20.2 40.4 sfdr (se) sfdr (de) sfdr C dbc figure 3. sfdr vs. f out @ f clock = 50 mhz (single-ended and differential) i out /ma 1.0 0.9 0.0 020 2 17.62 0.4 0.3 0.2 0.1 0.6 0.5 0.8 0.7 linearity vs. i out error linearity C lsbs figure 6. linearity vs. i out v aa = 5v 1 2 C5.0 C45.0 C85.0 0khz start 35.0mhz 70.0mhz stop sfdr C dbm clk = 140mhz f out = 20mhz sing o/p figure 9. single-tone sfdr @ f clock = 140 mhz (f out1 = 20 mhz) temperature C 8 c 72.0 71.8 70.4 C10 +25 +85 71.2 71.0 70.8 70.6 71.6 71.4 72.2 sfdr C dbc figure 4. sfdr vs. temperature @ f clock = 50 mhz (f out = 1 mhz) 1.00 0.50 C1.00 0.00 C0.50 code C inl 1023 0.75 C0.16 error C lsb figure 7. typical linearity v aa = 5v 1 C5.0 C45.0 C85.0 0khz start 35.0mhz 70.0mhz stop sfdr C dbc clk = 140mhz dual tone diff o/p 2 figure 10. dual-tone sfdr @ f clock = 140 mhz (f out1 = 13.5 mhz, f out2 = 14.5 mhz)
adv7127 C11C rev. 0 3 vCtypical performance characteristics (v aa = +3 v, v ref = 1.235 v, i out =17.62 m a, 50 v doubly terminated load, differential output loading, t a = +25 8 c) frequency C mhz 70 0 0.1 2.51 5.04 20.2 40.4 100 60 50 40 20 10 30 sfdr (se) sfdr (de) sfdr C dbc figure 11. sfdr vs. f out @ f clock = 140 mhz (single-ended and differential) frequency C mhz 76 74 56 0 160 50 100 140 68 62 60 58 72 70 64 66 4th harmonic 3rd harmonic 2nd harmonic thd C dbc figure 14. thd vs. f clock @ f out = 2 mhz (2nd, 3rd and 4th harmonics) v aa = 3.3v 1 C5.0 C45.0 C85.0 0khz start 35.0mhz 70.0mhz stop sfdr C dbm clk = 140mhz f out = 2.5mhz sing o/p 2 figure 17. single-tone sfdr @ f clock = 140 mhz (f out1 = 2 mhz) frequency C mhz 80 0 70 40 30 20 10 60 50 0.1 100 1.0 2.51 5.04 20.2 40.4 sfdr (se) sfdr (de) sfdr C dbc figure 12. sfdr vs. f out @ f clock = 50 mhz (single-ended and differential) i out C ma 1.0 0.9 0.0 020 2 17.62 0.4 0.3 0.2 0.1 0.6 0.5 0.8 0.7 linearity C lsbs figure 15. linearity vs. i out v aa = 3.3v 1 C5.0 C45.0 C85.0 0khz start 35.0mhz 70.0mhz stop sfdr C dbm clk = 140mhz f out = 20mhz sing o/p 2 figure 18. single-tone sfdr @ f clock = 140 mhz (f out1 = 20 mhz) temperature C 8 c 72.0 71.8 70.4 0 165 20 85 145 71.2 71.0 70.8 70.6 71.6 71.4 sfdr (f out = 1mhz) sfdr C dbc figure 13. sfdr vs. temperature @ f clock = 50 mhz, (f out = 1 mhz) 1.00 0.50 0.00 C0.50 0.75 1023 C0.42 error C lsb C1.00 codeC inl figure 16. typical linearity v aa = 3.3v 1 C5.0 C45.0 C85.0 0khz start 35.0mhz 70.0mhz stop sfdr C dbm clk = 140mhz dual tone sing o/p 2 figure 19. dual-tone sfdr @ f clock = 140 mhz (f out1 = 13.5 mhz, f out2 = 14.5 mhz)
adv7127 C12C rev. 0 circuit description and operation the adv7127 contains one 10-bit d/a converter, with one input channel containing a 10-bit register. a reference amplifier is also integrated on board the part. digital inputs ten bits of data (color information) d0Cd9 are latched into the device on the rising edge of each clock cycle. this data is pre- sented to the 10-bit dac and is then converted to an analog output waveform. see figure 20. clock data analog outputs , i out digital inputs d0Cd9 i out figure 20. video data input/output all these digital inputs are specified to accept ttl logic levels. clock input the clock input of the adv7127 is typically the pixel clock rate of the system. it is also known as the dot rate. the dot rate, and hence the required clock frequency, will be determined by the on-screen resolution, according to the following equation: dot rate = ( horiz res ) ( vert res ) ( refresh rate )/ ( retrace factor ) horiz res = number of pixels/line. vert res = number of lines/frame. refresh rate = horizontal scan rate. this is the rate at which the screen must be refreshed, typically 60 hz for a noninterlaced system or 30 hz for an interlaced system. retrace factor = total blank time factor. this takes into account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8). therefore, if we have a graphics system with a 1024 1024 resolution, a noninterlaced 60 hz refresh rate and a retrace factor of 0.8, then: dot rate = 1024 1024 60/0.8 = 78.6 mhz the required clock frequency is thus 78.6 mhz. all video data and control inputs are latched into the adv7127 on the rising edge of clock, as previously described in the digital inputs section. it is recommended that the clock input to the adv7127 be driven by a ttl buffer (e.g., 74f244). i out ma v 17.61 0.66 0 0 black level white level 100 ire figure 21. i out video output waveform table i. video output truth table (rset = 560 v , r load = 37.5 v ) description dac data i out i out input white level 17.62 0 3ff video video 17.62 C video data black level 0 17.62 000h power management the psave input of the adv7127 puts the part into standby mode. it is used to reduce power consumption. when psave is low, the power may be reduced to approximately 10 mw at 3 v. the adv7127 in tssop package also has a power-down feature where the entire p art, including the voltage reference circuit, is powered down. in this case, power on the adv7127 can be reduced to 60 m w at 3 v. table ii. power management mode adv7127 tssop adv7127 soic power-save 10 mw typically at 3 v 10 mw typically at 3 v power-down power 60 m w at 3 v not available reference input the adv7127 has an on-board voltage reference. the v ref pin is normally terminated to v aa through a 0.1 m f capacitor. alternatively, the part could, if required, be overdriven by an external 1.23 v reference (ad1580). a resistance r set connected between the r set pin and gnd determines the amplitude of the output video level according to the following equation: i out (ma) = 7,968 v ref (v)/r set ( w ) (1) using a variable value of r set , as shown in figure 22, allows for accurate adjustment of the analog output video levels. use of a fixed 560 w r set resistor yields the analog output levels as quoted in the specification page. these values typically correspond to the rs-343a video waveform values as shown in figure 21.
adv7127 C13C rev. 0 d/a converter the adv7127 contains a 10-bit d/a converter. the dac is designed using an advanced, high speed, segmented architec- ture. the bit currents corresponding to each digital input are routed to either the analog output (bit = 1) or gnd (bit = 0) by a sophisticated decoding scheme. the use of identical current sources in a monolithic design guarantees monotonicity and low glitch. the on-board operational amplifier stabilizes the full-scale output current against temperature and power supply variations. analog output the analog output of the adv7127 is a high impedance current source. the current output is capable of directly driving a 37.5 w load, such as a doubly terminated 75 w coaxial cable. figure 22 shows the required configuration for the output con- nected into a doubly terminated 75 w load. this arrangement will develop rs-343a video output voltage levels across a 75 w monitor. i out z o = 75 v (cable) z s = 75 v (source termination) z l = 75 v (monitor) dac figure 22. analog output termination for rs-343a a suggested method of driving rs-170 video levels into a 75 w monitor is shown in figure 23. the output current level of the dac remains unchanged, but the source termination resistance, z s , on the dac is increased from 75 w to 150 w . i out z o = 75 v (cable) z s = 150 v (source termination) z l = 75 v (monitor) dac figure 23. analog output termination for rs-170 more detailed information regarding load terminations for vari- ous output configurations, including rs-343a and rs-170, is available in an application note entitled video formats & required load terminations available from analog devices, publication no. e1228-15-1/89. figure 21 shows the video waveforms associated with the current output driving the doubly terminated 75 w load of figure 22. gray scale operation the adv7127 can be used for stand-alone, gray scale (mono- chrome) or composite video applications (i.e., only one channel used for video information). video output buffer the adv7127 is specified to drive transmission line loads, which is what most monitors are rated as. the analog output configurations to drive such loads are described in the analog interface section and illustrated in figure 23. however, in some applications it may be required to drive long transmission line cable lengths. cable lengths greater than 10 meters can attenu- ate and distort high frequency analog output pulses. the inclu- sion of output buffers will compensate for some cable distortion. buffers with large full power bandwidths and gains between two and four will be required. these buffers will also need to be able to supply sufficient current over the complete output voltage swing. analog devices produces a range of suitable op amps for such applications. these include the ad84x series of monolithic op amps. in very high frequency applications (80 mhz), the ad9617 is recommended. more information on line driver buffering circuits is given in the relevant op amp data sheets. use of buffer amplifiers also allows implementation of other video standards besides rs-343a and rs-170. altering the gain components of the buffer circuit will result in any desired video level. ad848 0.1 m f i out z 1 z 2 z o = 75 v (cable) z s = 75 v (source termination) z l = 75 v (monitor) dac 75 v Cv s +v s 0.1 m f gain (g) = 1 + z 1 z 2 figure 24. ad848 as an output buffer pc board layout considerations the adv7127 is optimally designed for lowest noise perfor- mance, both radiated and conducted noise. to complement the excellent noise performance of the adv7127 it is imperative that great care be given to the pc board layout. figure 25 shows a recommended connection diagram for the adv7127. the layout should be optimized for lowest noise on the adv7127 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should be minimized to inductive ringing. ground planes the adv7127 and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. this ground plane should connect to the regular pcb ground plane at a single point through a ferrite bead, as illustrated in figure 25. this bead should be located as close as possible (within 3 inches) to the adv7127. the analog ground plane should encompass all adv7127 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces and any output amplifiers. the regular pcb ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the adv7127.
adv7127 C14C rev. 0 power planes the pc board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. the analog power plane should encompass the adv7127 (v aa ) and all associated analog circuitry. this power plane should be con- nected to the regular pcb power plane (v cc ) at a single point through a ferrite bead, as illustrated in figure 25. this bead should be located within three inches of the adv7127. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7127 power pins, voltage reference circuitry and any output amplifiers. the pcb power and ground planes should not overlay portions of the analog power plane. keeping the pcb power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. supply decoupling noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see figure 25). optimum performance is achieved by the use of 0.1 m f ceramic capacitors. each of the two groups of v aa should be individually decoupled to ground. this should be done by placing the ca- pacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. it is important to note that while the adv7127 contains cir- cuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reducing power sup- ply noise. a dc power supply filter (murata bnx002) will pro- vide emi suppression between the switching power supply and the main pcb. alternatively, consideration could be given to using a three terminal voltage regulator. gnd r set i out ground adv7127 c3 0.1 m f c5 0.1 m f r1 75 v c1 33 m f c2 10 m f comp c6 0.1 m f analog power plane l2 (ferrite bead) d0 d9 clock video data inputs analog ground plane c4 0.1 m f l1 (ferrite bead) v aa v ref +5v (v cc ) r set 560 v component description vendor part number c1 33 m f tantalum capacitor c2 10 m f tantalum c3, c4, c5, c6 0.1 m f ceramic capacitor l1, l2 ferrite bead fair-rite 274300111 or murata bl01/02/03 r1 75 v 1% metal film resistor dale cmf-55c r set 560 v 1% metal film resistor dale cmf-55c video output psave pdown figure 25. typical connection diagram and component list
adv7127 C15C rev. 0 digital signal interconnect the digital signal lines to the adv7127 should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the adv7127 should be avoided so as to minimize noise pickup. any active pull-up termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ), and not the analog power plane. analog signal interconnect the adv7127 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high fre- quency power supply rejection. for optimum performance, the analog outputs should each have a source termination resistance to ground of 75 w (doubly terminated 75 w configuration). this termination resistance should be as close as possible to the adv7127 so as to mini- mize reflections. additional information on pcb design is available in an applica- tion note entitled design and layout of a video graphics system for reduced emi. this application note is available from analog devices, publication number e1309-15-10/89.
C16C c3259C8C4/98 printed in u.s.a. adv7127 rev. 0 28-lead soic (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc

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